In IC fabrication, metal structures and metal layers are used extensively as conducting paths in the circuit. Indeed, multiple levels of metal layers (above an underlying substrate) are typically employed when manufacturing the IC. The multiple metal layers are employed in order to accommodate higher densities, allowing device dimensions to shrink well below one micron. Thus, ICs having three and four levels (and more) of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
One common metal used for forming such metal layers (also referred to as metal lines or metal wiring) is Tungsten (W). Tungsten is also used as a material for forming interconnections in vias to connect the different metal layers. The size (e.g., width) of the tungsten structures typically ranges from “large” structures (with the smallest dimension greater than about 1 microns) to “small” structures (with the smallest dimension less than about 0.25 microns). As the size of ICs decrease, even smaller metal structures will necessarily be used.
As with other IC fabrication methods, devices containing metal structures are often subjected to heat treatments. Such heat treatments can often cause problems with the metal structures. See, for example, U.S. Pat. No. 6,184,118, the disclosure of which is incorporated herein by reference. In particular, tungsten structures can often “peel” during heat treatments and especially during aggressive heat treatments, e.g., those lasting for about 1 minute at a temperature of about 800° C. When the tungsten structures delaminate or peel, they can cause electrical failure in that wafer die where the peeling occurs. As well, such peeling can also cause high defect densities in adjacent dies on the wafer since the peeled metal can move to adjacent dies. Finally, such peeling can contaminate fabrication equipment, resulting in widespread defect problems.
To overcome this problem, many manufacturers employ very strict topological design requirements, even if they do not use aggressive heat treatments. For example, some manufacturers will not make tungsten structures with dimensions greater than 1 micron because of the problems noted above. Without larger tungsten structures, many IC devices can be limited in their features and functionality. For example, slotting or waffling techniques are often used to meet maximum size requirements while providing wider (lower resistance) metal lines. Such techniques, however, can make the total size of high-current-carrying structures, such as bus lines, larger than if no slotting was needed. Also, it is often difficult to use such techniques within areas of the wafer having irregular circuit features.